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ASAHI KASEI
[AK4382A]
AK4382A
112dB 192kHz 24-Bit 2ch DAC
ST --v
AK4382AIfBW^I*[fBI@Si--pERXgptH*[}"X*1/2 24rbgDACA**B _ * } * | (SCF)*I--pAe*AN*bNWb^ Eaee*"xI--ou`PU**BT"vS"OOE*[gI 192kHzUA`IAe*A DVD, AC-3A"v "TMIVXeE*A"KA**B K4382AI '*OE^ A 16pin TSSOPpbP*[WEZA`*e*ASi"AXy*[X*i OEU**B
"A '*
o T"vS"OOE*[g 192kHz : 8kHz o 128 "{I*[oT"vS"O*i'E*i`*[h*j o 64 "{I*[oT"vS"O*i 2"{`*[h*j o 32 "{I*[oT"vS"O*i 4"{`*[h*j o 24 rbg8 "{ FIR fBW^tB^"a` o SCF "a` o fBW^fBG"t@VX"a` (32kHz, 44.1kHz, 48kHz `I ) o \tg~...*[g"a` o fBW^ ATT (256Xebv ) o fBW^ tH*[}bg24rbg`Ol, 24/20/16rbgOEal I2S I/F : , : 256fs, 384fs, 512fs or 768fs*i'E*i`*[h*j o }X^N*bN 128fs, 192fs, 256fs or 384fs*i2"{`*[h*j 128fs or 192fs*i4"{`*[h*j o THD+N: -94dB o Dynamic Range: 112dB o -Wb^`I--I o "dOE"d 4.75 5.25V : o '*OE^pbP*[W : 16pin TSSOP (6.4mm x 5.0mm)
MCLK VDD CSN CCLK CDTI
P Interface
De-emphasis Control
Clock Divider
VSS DZFL DZFR
LRCK BICK SDTI
Audio Data Interface
8X Interpolator 8X Interpolator
Modulator Modulator
AOUTL+
SCF
AOUTLAOUTR+
SCF
AOUTR-
PDN
MS0071-J-01 -1-
2002/2
ASAHI KASEI
[AK4382A]
n I*[_S"OKCh
AK4382AVT AKD4382 -40 +85C 16pin TSSOP (0.65mm pitch) AK4382A --p*]{*[h
n s""z'u
MCLK BICK SDTI LRCK PDN CSN CCLK CDTI 1 2 3 4 5 6 7 8 16 15 14 DZFL DZFR VDD VSS AOUTL+ AOUTLAOUTR+ AOUTR-
Top View
13 12 11 10 9
s"*^@"\ Function Master Clock Input Pin An external TTL clock should be input on this pin. 2 BICK I Audio Serial Data Clock Pin 3 SDTI I Audio Serial Data Input Pin 4 LRCK I L/R Clock Pin 5 PDN I Power-Down Mode Pin When at "L", the AK4382A is in the power-down mode and is held in reset. The AK4382A should always be reset upon power-up. 6 CSN I Chip Select Pin 7 CCLK I Control Data Input Pin 8 CDTI I Control Data Input Pin 9 AOUTRO Rch Negative Analog Output Pin 10 AOUTR+ O Rch Positive Analog Output Pin 11 AOUTLO Lch Negative Analog Output Pin 12 AOUTL+ O Lch Positive Analog Output Pin 13 VSS Ground Pin 14 VDD Power Supply Pin 15 DZFR O Rch Data Zero Input Detect Pin 16 DZFL O Lch Data Zero Input Detect Pin Note: All input pins should not be left floating. No. 1 Pin Name MCLK I/O I
MS0071-J-01 -2-
2002/2
ASAHI KASEI
[AK4382A]
*a`I*A`a'eSi (VSS=0V; Note 1) Parameter Symbol Power Supply VDD Input Current (any pins except for supplies) IIN Input Voltage VIND Ambient Operating Temperature Ta Storage Temperature Tstg Note: 1. "dI*xAO"hs"E`I*e'lA**B
min -0.3 -0.3 -40 -65
max 6.0 10 VDD+0.3 85 150
Units V mA V C C
'*O: I'l'|1/2*OE*AZg--p1/2*e**AfoCX"jo*eAE eU**B U1/2'E*iI"(R)*iI*U*OeUn*B
**"(R)*i*OE* (VSS=0V; Note 1) Parameter Power Supply Symbol VDD min 4.75 typ 5.0 max 5.25 Units V
'*O: -{f*[^V*[gEL*UeAe*OE*ESOIZg--pESOAI*A"-ZAI*O"C*(c)EU*IA*\* '*O*B
MS0071-J-01 -3-
2002/2
ASAHI KASEI
[AK4382A]
Ai*O"A* ("ALE*e*I*A = 25C; VDD = 5.0V; fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; Ta 24bit Input Data; Measurement frequency = 20Hz 20kHz; RL 2k) Parameter min typ max Units Resolution 24 Bits Dynamic Characteristics (Note 3) THD+N fs=44.1kHz 0dBFS -94 -86 dB BW=20kHz -60dBFS -48 dB fs=96kHz 0dBFS -92 -84 dB BW=40kHz -60dBFS -45 dB fs=192kHz 0dBFS -92 dB BW=40kHz -60dBFS -45 dB Dynamic Range (-60dBFS with A-weighted) (Note 4) 102 112 dB S/N (A-weighted) (Note 5) 102 112 dB Interchannel Isolation (1kHz) 90 110 dB Interchannel Gain Mismatch 0.2 0.5 dB DC Accuracy Gain Drift 100 ppm/C Output Voltage (Note 6) Vpp 2.55 2.75 2.95 Load Resistance (Note 7) 2 k Power Supplies Power Supply Current (VDD) 20 34 mA Normal Operation (PDN = "H", fs96kHz) 25 42 mA Normal Operation (PDN = "H", fs=192kHz) 10 100 A Power-Down Mode (PDN = "L") (Note 8) Notes: 3. Audio Precision (System Two)Zg--p*B`'eOEEI*]{*[hI}j...AZQ*AE*B 4. 100dB at 16bit data. 5. S/N"aI"u--Irbg'*EE`Un*B 6. tXP*["d (0dB)*B*o--I"dIVDD I"dE"a--aU**B AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = 2.75VppxVDD/5*B 7. AC*xE`IA*B DC*x e*e*ISk 8. N*bN (MCLK, BICK, LRCK)SU`SfBW^"u--Is" VDD U1/2I VSS EOEA 'e1/2*e*I 'lA**B
MS0071-J-01 -4-
2002/2
ASAHI KASEI
[AK4382A]
V*[v**[It*EtB^"A* (Ta = 25C; VDD = 4.75 5.25V; fs = 44.1kHz; DEM = OFF; SLOW = "0") Parameter Symbol min Digital filter PB 0 Passband 0.05dB (Note 9) -6.0dB Stopband (Note 9) SB 24.1 Passband Ripple PR Stopband Attenuation SA 54 Group Delay (Note 10) GD Digital Filter + SCF Frequency Response 20.0kHz fs=44.1kHz FR 40.0kHz fs=96kHz FR 80.0kHz fs=192kHz FR -
typ
max 20.0 0.02
Units kHz kHz kHz dB dB 1/fs
22.05
19.3
-
dB 0.2 dB 0.3 dB +0/-0.6 Notes: 9. 'Eae*A`jZ~aeIZu"g*"I (VXeT"vS"OOE*[g fs ) E"a--a*A PB=0.4535*fs(@0.05dB)*A SB=0.546*fs A**B 10. fBW^tB^EaeeZZ'xA*A 16/24rbgf*[^"u--IOEWX^EZbgeA(c)cAi *O*M**o--IeeUAIZSOA**B X**[**[It*EtB^"A* (Ta = 25C; AVDD, DVDD = 4.75~5.25V; fs = 44.1kHz; DEM = OFF; SLOW = "1") Parameter Digital Filter Passband 0.04dB -3.0dB (Note 11) (Note 11) PB SB PR SA GD 0 39.2 72 18.2 8.1 0.005 19.3 +0/-5 +0/-4 +0/-5 kHz kHz kHz dB dB 1/fs dB dB dB Symbol min typ max Units
Stopband Passband Ripple Stopband Attenuation Group Delay Digital Filter + SCF Frequency Response
(Note 10)
FR 20.0kHz fs=44.kHz 40.0kHz fs=96kHz FR fs=192kHz 80.0kHz FR Note: 11. The passband and stopband frequencies scale with fs. For example, PB = 0.185xfs (@0.04dB), SB = 0.888xfs.
DC"A*
(Ta = 25C; VDD = 4.75 5.25V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout = -80A) Low-Level Output Voltage (Iout = 80A) Input Leakage Current Symbol VIH VIL VOH VOL Iin min 2.2 VDD-0.4 typ max 0.8 0.4 10 Units V V V V A
MS0071-J-01 -5-
2002/2
ASAHI KASEI
[AK4382A]
XCb"O"A* (Ta = 25C; VDD = 4.75 5.25V; CL = 20pF) Parameter Master Clock Frequency Duty Cycle LRCK Frequency Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle Audio Interface Timing BICK Period Normal Speed Mode Double/Quad Speed Mode BICK Pulse Width Low Pulse Width High BICK "" to LRCK Edge (Note 12) LRCK Edge to BICK "" (Note 12) SDTI Hold Time SDTI Setup Time Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN High Time CSN "" to CCLK "" CCLK "" to CSN "" Reset Timing PDN Pulse Width (Note 13) Symbol fCLK dCLK fsn fsd fsq Duty min 2.048 40 8 60 120 45 typ 11.2896 max 36.864 60 48 96 192 55 Units MHz % kHz kHz kHz %
tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tPD
1/128fs 1/64fs 30 30 20 20 20 20 200 80 80 40 40 150 50 50 150
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 12. IKSi'lI LRCK IGbWAE BICK I "" *dEcEaeEK'eAU**B 13. "dOE"S"uZI DN "L" (c)c "H" E*eAEASZbg(c)(c)eU**B P
MS0071-J-01 -6-
2002/2
ASAHI KASEI
[AK4382A]
n ^C~"O"gOE
1/fCLK VIH VIL tCLKH tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
MCLK
1/fs VIH VIL
LRCK
tBCK VIH VIL tBCKH tBCKL Clock Timing
BICK
LRCK tBLR tLRB
VIH VIL
BICK tSDS tSDH
VIH VIL
SDTI
VIH VIL
Serial Interface Timing
MS0071-J-01 -7-
2002/2
ASAHI KASEI
[AK4382A]
VIH CSN VIL tCSS tCCKL tCCKH VIH VIL tCDS tCDH VIH VIL
CCLK
CDTI
C1
C0
R/W
A4
WRITE Command Input Timing
tCSW VIH CSN VIL tCSH CCLK VIH VIL
CDTI
D3
D2
D1
D0
VIH VIL
WRITE Data Input Timing
tPD
PDN
VIL
Power-down Timing
MS0071-J-01 -8-
2002/2
ASAHI KASEI
[AK4382A]
@"\*a-3/4
n VXeN*bN *K--vEN*bNI*A LRCK, BICK A**B}X^N*bN MCLK, (MCLK) AET"vS"ON*bN (LRCK) I
"Su*e*K--vI eU*E`S*ie*K--vI eUn*B MCLK IC"^|*|OE*[V"tB^AE *I'SiEZg--peU**B MCLKZu"g*"*Y'e*e*u-@I"a*"OEWX^A*Y'e*e*u-@ (Manual Setting Mode) AEfoCX"a*"AZ(c)"(R)*Y'e*e*u-@ (Auto Setting Mode) IQA eU**B Manual Setting Mode (ACKS = "0": Register 00H)AI*A DFS0/1 AT"vS"OXs*[h*Y'ee (Table 1)*ASeXs*[hAI CLKZu"g*"IZ(c)"(R) M *Y'eeU* (Table 2~4)*BSZbg*oeZ = "") I Auto Setting Mode E*Y'eeU**B Auto Setting Mode (PDN (ACKS = "1": Default) AI*AT"vS"OXs*[hAECLKZu"g*"IZ(c)"(R)OEY*oe M (Table 5)*A"a*"N*bNI "K*OEZu"g*" (Table 6) EZ(c)"(R)*Y'eee1/2*A DFS0/1I*Y'eI*s--vA**B "(R)*iZ (PDN= "H") I*ASeSO*"N*bN (MCLK, BICK, LRCK) Z~AIUn*BecIN*bNY eE*e**A"a*"E_Ci~bNE*WbNZg--pAe1/2*A"d----e*A"(R)*iU*iEEeA "\* eU**BN*bNZ~e*e*Ip**[_E"*o`O (PDN= "L") EA*B"dOEON "TMISZb g*oeZ = "") I MCLK, LRCK "u--IeeUAp**[_E"*o`OA**B (PDN
DFS1 0 0 1
DFS0 0 1 0
Sampling Rate (fs) Normal Speed Mode Double Speed Mode Quad Speed Mode 8kHz~48kHz 60kHz~96kHz 120kHz~192kHz Default
Table 1.T"vS"OXs*[h (Manual Setting Mode)
LRCK fs 32.0kHz 44.1kHz 48.0kHz
256fs 8.1920MHz 11.2896MHz 12.2880MHz
MCLK 384fs 512fs 12.2880MHz 16.3840MHz 16.9344MHz 22.5792MHz 18.4320MHz 24.5760MHz
768fs 24.5760MHz 33.8688MHz 36.8640MHz
BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz
Table 2. VXeN*bN--a (Normal Speed Mode *-- Manual Setting Mode)
LRCK fs 88.2kHz 96.0kHz
128fs 11.2896MHz 12.2880MHz
MCLK 192fs 256fs 16.9344MHz 22.5792MHz 18.4320MHz 24.5760MHz
384fs 33.8688MHz 36.8640MHz
BICK 64fs 5.6448MHz 6.1440MHz
Table 3. VXeN*bN--a (Double Speed Mode *-- Manual Setting Mode)
LRCK fs 176.4kHz 192.0kHz
MCLK 128fs 22.5792MHz 24.5760MHz 192fs 33.8688MHz 36.8640MHz
BICK 64fs 11.2896MHz 12.2880MHz
Table 4. VXeN*bN--a Speed Mode *-- (Quad Manual Setting Mode)
MS0071-J-01 -9-
2002/2
ASAHI KASEI
[AK4382A]
MCLK 512fs 768fs 256fs 384fs 128fs 192fs
Sampling Speed Normal Double Quad
Table 5. T"vS"OXs*[hAuto Setting Mode: Default) (
LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz
128fs 22.5792 24.5760
192fs 33.8688 36.8640
MCLK (MHz) 256fs 384fs 22.5792 33.8688 24.5760 36.8640 -
512fs 16.3840 22.5792 24.5760 -
768fs 24.5760 33.8688 36.8640 -
Sampling Speed Normal Double Quad
Table 6. VXeN*bN--a Setting Mode) (Auto
n I*[fBIVSAC"^tF*[XtH*[}bg I*[fBIf*[^I BICK AELRCK ZgAA SDTI (c)c"u--IeU**B 5 Zi--ItH*[}bg(Table 7)
DIF0-2A`I`AU**B`S*[hAEa MSB t@*[Xg*A R"vS*"gIf*[^tH*[}bgA BICK I 2's --*aeAbeU**B Mode 2 16/20rbgAZgA1/2*e*If*[^IE LSB EI "0" "u--IA *B Mode 0 1 2 3 4 DIF2 0 0 0 0 1 DIF1 0 0 1 1 0 DIF0 0 1 0 1 0 SDTI Format 16bit OEal 20bit OEal 24bit `Ol 24bit I2S OEYS* 24bit OEal BICK 32fs 40fs 48fs 48fs 48fs Figure Figure 1 Figure 2 Figure 3 Figure 4 Figure 2
Default
Table 7. I*[fBIf*[^tH*[}bg
MS0071-J-01 - 10 -
2002/2
ASAHI KASEI
[AK4382A]
LRCK
0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1
BICK (32fs) SDTI Mode 0
0
15
1
14
6
14
5
15
4
16
3
17
2
1
31
0
0
15
1
14
6
14
5
15
4
16
3
17
2
1
31
0
15
0
14
1
BICK (64fs) SDTI Mode 0
Don't care 15:MSB, 0:LSB 15 14 0 Don't care 15 14 0
Lch Data
Figure 1. Mode 0 Timing
Rch Data
LRCK
0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 0 1
BICK (64fs) SDTI Mode 1 SDTI Mode 4
Don't care 19:MSB, 0:LSB Don't care 23 22 21 20 19 0 Don't care 23 22 21 20 19 0 19 0 Don't care 19 0
23:MSB, 0:LSB
Lch Data
Figure 2. Mode 1,4 Timing
Rch Data
LRCK
0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1
BICK (64fs) SDTI
23 22 23:MSB, 0:LSB 1 0 Don't care 23 22 1 0 Don't care 23 22
Lch Data
Figure 3. Mode 2 Timing
Rch Data
MS0071-J-01 - 11 -
2002/2
ASAHI KASEI
[AK4382A]
LRCK
0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1
BICK (64fs) SDTI
23 22 23:MSB, 0:LSB 1 0 Don't care 23 22 1 0 Don't care 23
Lch Data
Figure 4. Mode 3 Timing
Rch Data
n fBG"t@VXtB^
IIR tB^Eaee 3 Zu"g*"(32kHz, 44.1kHz, 48kHz) `IIfBG"t@VXtB^ (50/15s "A* "a` ) AU**B Double Speed Mode, Quad Speed ModeIAE*AfBG"t@VXtB^IOFFA**B DEM1 0 0 1 1 DEM0 0 1 0 1 Mode 44.1kHz OFF 48kHz 32kHz Default
Table 8. fBG"t@VXR"g**[ (Normal Speed Mode)
n *o--I{S...*[
AK4382AI MUTESUSjAXebv*A OExIl"AE--fBW^*o--I{S...*[*i 256 ATT*j"a ` U**BI{S...*[I DACI`O'iE e"u--If*[^ 0dB(c)c -48dBUAAel*[V"*AU1/2I~... *[gU**B*Y'e'lSOI`JUI\tg`JUA**B*]AA*A`JU'EXCb"OmCYI"-*Un*B 1 OE x*I1/2AEI`JUZSOAE OEx`S`II`JUZSO Table 9EZ|U**B 256 Sampling Speed Normal Speed Mode Double Speed Mode Quad Speed Mode 1 Level 4LRCK 8LRCK 16LRCK Table 9. ATT`JUZSO `JUZSO 255 to 0 1020LRCK 2040LRCK 4080LRCK
MS0071-J-01 - 12 -
2002/2
ASAHI KASEI
[AK4382A]
n [*OEY*o@"\
AK4382AIl"AE--I[*OEY*o@"\Z*U**BSelI"u--If*[^ 8192nA`A"0"I*e**A SelI DZFs""AE--E"H"EEeU**BIOEaSelI"u--If*[^ "0"AE-EeAE`I*e lI DZFs" "L"EEeU**B RSTNrbg "0"I*e**A--1/4lI DZFs " "H"EEeU**B RSTNrbg "1"EEA1/2OEaSelI"u--If*[^ "0"AE-EeAE`I*elI DZFs" 4~5LRCKOEaE"L"EEeU**BU1/2*A DZFMrbg "1"E*eAE--1/4lI"u--If*[^ 8192nA`A "0"I*e*IY--1/4lI DZFs" "H"EEeU**B[*OEY*o@"\I ZFErbgA-OEoEAU**BI D AE--1/4lIDZFs"I*iE "L"A**BDZFs"IE*I DZFBrbgA"1/2"]*eAEA"\A**B
n \tg~...*[g@"\
\tg~...*[gIfBW^"IEZA*seU**B SMUTErbg "1"E*eAEIZ"_I ATT*Y'e'l(c)c ATT*Y'e'l xATT`JUZSO (Table 9)A"u--If*[^ - ("0")UAAel*[V"eU**B SMUTErbg "0" E*eAE*A- TM - TT*Y'e'l xATT`JUZSOA TT*Y'e'lUA*oeAU**B\tg~...*[ A A gSJZnOEa*A [ - [ ATT *Y'e'lUA*oeAU**B\tg~...*[g@"\I*M*Z~E*M*OE*Oe`O|e*e*ECE--L OEoA**B
SMUTE bit (1) (1) (3)
ATT Level Attenuation
-
GD (2) AOUT (4) 8192/fs GD
DZF pin
'*: (1) ATT*Y'e'lxATT`JUZSO (Table 9) *B--a|I*Aormal Speed ModeZ*A N ATT*Y'e'l "255"I*e*I 1020LRCKTCNA**B (2) fBW^"u--IE`IAAi*O*o--IIOEQ'x (GD)Z*U**B (3) \tg~...*[gSJZnOEa*A [ - [ 0dBUA*oeAU**B (4)"u--If*[^--1/4lAEaE8192nA`A "0"I*e**A ZFs"I "H"EEeU**B D IOEa"u--If*[^ "0"AE-EeAE*ADZFs"I*(R)E "L"EEeU**B Figure 5. \tg~...*[g@"\AE[*OEY*o@"\
MS0071-J-01 - 13 -
2002/2
ASAHI KASEI
[AK4382A]
n VXeSZbg
"dOE ON ZEI*A PDNs"Ee"x "L" "u--IASZbgA* SZbgyNp**[_E"IMCLK A B *oee*IOEaLRCK I "" E"SuA"a*"nHp**[Abv*"a*"I^C~"O"(R)*iU**B A A LRCK "u--IeeUAp**[_E"*o`OA**B
n p**[_E"@ "\
PDNs" *g E*eAEp**[_E"*o`OEEe*AAi*O*o--IIt**[eB"O*o`O EEeU**B L" (Hi-Z) Figure5 Ep**[_E"yNp**[AbvZIVXe^C~"O--aZ|U**B
PDN
Internal State D/A In (Digital)
GD
Normal Operation
Power-down
Normal Operation
"0" data
(1)
GD
D/A Out (Analog)
Clock In
MCLK, LRCK, BICK
(3) (4)
(2)
(3)
(1)
Don't care
DZF External MUTE
(6)
(5)
Mute ON
'**F (1) fBW^"u--IE`IAAi*O*o--IIOEQ'x Z*U**B (GD) (2) p**[_E"ZAi*O*o--II A**B Hi-Z (3) PDN*M*IGbW ") ANSbNmCY*o--IeU**B (" ImCYIf*[^ "0" I*e*Aa*o--IeU**B (4) p**[_E"*o`O (PDN = "L")AISeN*bN"u--I (MCLK, BICK, LRCK) Z~eAEAU**B (5) NSbNmCY -a`eEEe*e*I*AAi*O*o--ISO*"A~...*[gA*B (3) (6) p**[_E"*o`O (PDNs" = "L")AI*A DZFs"I "L"EEeU**B Figure 6. p**[_E"p**[AbvZ^C~"O--a /
MS0071-J-01 - 14 -
2002/2
ASAHI KASEI
[AK4382A]
n SZbg@"\
RSTNrbg *g 0"E*eAE*ADACISZbgeU**A"a*"OEWX^I *SueUn*BIZAi* O*o--II VCOM "dEEe*A DZFL/DZFRs"I "H"EEeU**B Figure 7ERSTNrbgEaeeSZbgV*[ P"XZ|U**B RSTN bit
3~4/fs (6) 2~3/fs (6)
Internal RSTN bit Internal State D/A In (Digital) (1) D/A Out (Analog)
Clock In
MCLK,LRCK,BICK
Normal Operation
Digital Block Power-down
Normal Operation
"0" data GD GD
(3)
(2) (4)
Don't care
(3)
(1)
2/fs(5)
DZF
'**F
(1) fBW^"u--IE`IAAi*O*o--IIOEQ'x (GD)Z*U**B (2) RSTN = "0"ZAi*O*o--II VCOM"d (VDD/2)A**B (3) "a*" RSTN*M*IGbW ")ANSbNmCY*o--IeU**BImCYIf*[^"0"I*e*A (" a*o--IeU**B (4) SZbg*o`O (RSTN = "0")AISeN*bN"u--I (MCLK, BICK, LRCK)Z~eAEAU**B (5) DZFs"I RSTNrbgI--eGbWA"H"EEe*A LSI"a*"I RSTNrbgI--*aeGbW I 2/fsOEa"L"EEeU**B (6) RSTNrbg*`*nA(c)cLSI"a*"I RSTNrbg*I*eUAI--eZE 3 ~4/fs (c)(c)e U**BU1/2*A--*aeZE 3/fs(c)eU**B 2~ Figure 7. SZbg^C~"O--a
MS0071-J-01 - 15 -
2002/2
ASAHI KASEI
[AK4382A]
n *[hR"g**[C"^tF*[X
AK4382A ISe@"\IOEWX^A*Y'eAU**BOEWX^*Y'e I 3*uZ(R)VSA s" : CSN, CCLK, CDTI A I/F *`*Y*sU**B I/F*aIf*[^I Chip address (2bit, C1/0, "01"OEA'e, Read/Write (1bit, "1"OEA'e Write only), ) , Register address (MSB first, 5bit) AEControl data (MSB first, 8bit)A*\*eU**Bf*[^`--*M`ICCLKI "" A Serbg*o--I*AZo*M`I AZaee*YU**Bf*[^I*`*YI "" CSNI ""A--LOEoEEeU**B CCLK IN*bNXs*[hI MHz (max)A**BANZXEAEI SN I "H"EOEA'eA*B 5 C PDNs" "L"E*eAE"a*"OEWX^'lI*SueU**BU1/2*A RSTNrbgE "L"*`*AE"a*"^C ~"OnHSZbgeU**B'A*AIAEOEWX^I"a--eI*SueUn*B
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: R/W: A4-A0: D7-D0:
Chip Address (Fixed to "01") READ/WRITE (Fixed to "1", Write only) Register Address Control Data
Figure 8. Control I/F Timing *AK4382AIf*[^"CY*YT|*[gUn*BU1/2*A 1/0, R/W IOEA'e ("011") A**B C *PDN = "L"Z*AaeN}X^N*bNYeAEZI*AR"g**[OEWX^OI*`*YIA Un*B
n Register Map
Addr 00H 01H 02H 03H 04H Notes: For addresses from 05H to 1FH, data must not be written. When PDN pin goes "L", the registers are initialized to their default values. When RSTN bit goes "0", the only internal timing is reset and the registers are not initialized to their default values. All data can be written to the register even if PW or RSTN bit is "0". Register Name Control 1 Control 2 Control 3 Lch ATT Rch ATT D7 ACKS DZFE 0 ATT7 ATT7 D6 0 DZFM 0 ATT6 ATT6 D5 0 SLOW 0 ATT5 ATT5 D4 DIF2 DFS1 0 ATT4 ATT4 D3 DIF1 DFS0 0 ATT3 ATT3 D2 DIF0 DEM1 DZFB ATT2 ATT2 D1 PW DEM0 0 ATT1 ATT1 D0 RSTN SMUTE 0 ATT0 ATT0
MS0071-J-01 - 16 -
2002/2
ASAHI KASEI
[AK4382A]
n Register Definitions
Addr 00H Register Name Control 1 default D7 ACKS 1 D6 0 0 D5 0 0 D4 DIF2 0 D3 DIF1 1 D2 DIF0 0 D1 PW 1 D0 RSTN 1
RSTN: Internal timing reset control 0: Reset. All registers are not initialized. 1: Normal Operation When MCLK frequency or DFS changes, the AK4382A should be reset by PDN pin or RSTN bit. PW: Power down control 0: Power down. All registers are not initialized. 1: Normal Operation DIF2-0: Audio data interface formats (see Table 7) Initial: "010", Mode 2 ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode Master clock frequency is detected automatically at ACKS bit "1". In this case, the setting of DFS1-0 are ignored. When this bit is "0", DFS1-0 set the sampling speed mode.
Addr 01H
Register Name Control 2 default
D7 DZFE 0
D6 DZFM 0
D5 SLOW 0
D4 DFS1 0
D3 DFS0 0
D2 DEM1 0
D1 DEM0 1
D0 SMUTE 0
SMUTE: Soft Mute Enable 0: Normal operation 1: DAC outputs soft-muted DEM1-0: De-emphasis Response (see Table 8) Initial: "01", OFF DFS1-0: Sampling speed control 00: Normal Speed Mode 01: Double Speed Mode 10: Quad Speed Mode When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs. SLOW: Slow Roll-off Filter Enable 0: Sharp Roll-off Filter 1: Slow Roll-off Filter DZFE: Data Zero Detect Enable 0: Disable 1: Enable Zero detect function can be disabled by DZFE bit "0". In this case, the DZF pins of both channels are always "L".
MS0071-J-01 - 17 -
2002/2
ASAHI KASEI
[AK4382A]
DZFM: Data Zero Detect Mode 0: Channel Separated Mode 1: Channel ANDed Mode If the DZFM bit is set to "1", the DZF pins of both channels go to "H" only when the input data at both channels are continuously zeros for 8192 LRCK cycles.
Addr 02H
Register Name Control 3 default
D7 0 0
D6 0 0
D5 0 0
D4 0 0
D3 0 0
D2 DZFB 0
D1 0 0
D0 0 0
DZFB: Inverting Enable of DZF 0: DZF goes "H" at Zero Detection 1: DZF goes "L" at Zero Detection
Addr 03H 04H
Register Name Lch ATT Rch ATT default
D7 ATT7 ATT7 1
D6 ATT6 ATT6 1
D5 ATT5 ATT5 1
D4 ATT4 ATT4 1
D3 ATT3 ATT3 1
D2 ATT2 ATT2 1
D1 ATT1 ATT1 1
D0 ATT0 ATT0 1
ATT = 20 log10 (ATT_DATA / 255) [dB] 00H: Mute
VXe*YOEv VXe*U`--a Figure 9 EZ|U**Bi`I"IEnHAE`'e--aEAAI*]--p{*[h (AKD4382) ZQ*AE A*B
Master Clock 64fs 24bit Audio Data fs Reset & Power down Microcontroller
1 2 3 4 5 6 7 8
MCLK BICK SDTI LRCK PDN CSN CCLK CDTI
DZFL DZFR VDD
16 15 14 0.1u 13 12 11 10 9 + 10u
Analog Supply 5V
Lch MUTE Rch MUTE
AK4382A
VSS AOUTL+ AOUTLAOUTR+ AOUTR-
Lch LPF Rch LPF
Lch Out MUTE Rch Out
Digital Ground
Analog Ground
Figure 9. Typical Connection Diagram Notes: - LRCK = fs, BICK=64fs. - AOUT--e--E**xi"(R)*e*e*I'1/4--nE'i*R"ueA*B - v_E"s"ESOI"u--III*[v"EEA*B
MS0071-J-01 - 18 -
2002/2
ASAHI KASEI
[AK4382A]
1. O"hAE"dOEIfJbvS"O
VDD AE VSS EIVXeIAi*O"dOEY*AVXeIfBW^"dOEAEI*--A*BU1/2*A VDD IfJbvS"OR"f"T*A"AE*--e--EIZ~bNR"f"TIAe3/4AA*U`U**B VDD s"AE VSS s"I"dI**Ai*O*o--IOE"W*Y'eU**B
* 2. Ai*Oo--I
Ai*O*o--IIS(R)`S**"(R)*o--IEEAAe*A*o--IOE"WI 2.5V'*SE 0.55 x VDD Vpp (typ)*B**"(R)*o--IISO *"AAZZeU**BAOUT+ AE AOUT-IAZZ"dIVAOUT = (AOUT+)-(AOUT-)A**BAZZQC"PI*e**A *o--IOE"WI 5.5Vpp (typ@VDD=5V)A**BSO*"AZZnHIoCAX"dISO*"AYeU**B"u--IR*[h ItH*[}bgI 2's R"vS*"g(2 I*a*" ) A7FFFFFH(@24bit) E`IAI*ItXP*[*A 800000H(@24bit) E`IAI*ItXP*[*A 000000H(@24bit) AI VAOUTI--*`z'lI 0V "d*o--IeU **B "a` I [ SCF*jA OE*SeU**BAK4382AI**"(R)*o--IA e1/2 DCJbg--pLpV^EA AOUT+/-I DCItZbg*oe Z*eAEA"\A**B Figure 10AE 11I**"(R)*o--IIyA"vAAZZ*eSO*" nH--aA**B LPF
4.7k 4.7k R1 470p
AOUTVop
3300p 4.7k R1
AOUT+
Vop
1k
Analog Out
4.7k
470p
BIAS
47u
0.1u When R1=200 fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz When R1=180 fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
1k
Figure 10. External 2nd order LPF Circuit Example (using op-amp with single power supply)
4.7k 4.7k R1 470p
AOUT+Vop
3300p 4.7k R1
AOUT+
Analog Out
-Vop
4.7k
470p
When R1=200 fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz When R1=180 fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
Figure 11. External 2nd order LPF Circuit Example (using op-amp with dual power supplies)
MS0071-J-01 - 19 -
2002/2
ASAHI KASEI
[AK4382A]
pbP*[W
16pin TSSOP (Unit: mm)
*5.00.1 1.050.05
16
9 *4.40.1 A 6.40.2 0.170.05 Detail A 0.10.1 0-10 0.50.2 0.10
G|LVOEnZ/Z " "1/4"c(-" )*bL 2002/2 - 20 -
1 0.220.1
8 0.65
0.13 M
Seating Plane
NOTE: Dimension "*" does not include mold flash.
n *Z*E*bLZd--l
pbP*[W*Z : S*[htOE*[*Z : S*[htOE*[*--* :
MS0071-J-01
ASAHI KASEI
[AK4382A]
}*[L"O
AKM 4382AT XXYYY
1) 2)
3) 4)
Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 4382AT Asahi Kasei Logo
*d--vE'*OZ-* *{
* * *
* *
* *] { { }(R) * ... * (c) { ( ) * * * (c) xTM (R) ...TM (R)/ * / (c) (c) (c) / / (c) ] (c) /(c) (R) / *
MS0071-J-01 - 21 -
2002/2

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